USB 3.2 PHY(Host/Device/OTG/Hub)

The Innosilicon USB3.2 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for USB3.2 standard from Intel. The PHY supports USB3.2 physical layer specifications.

KEY FEATURES:

  • Supports 5/10Gbps serial data transmission rate

  • Allows integration of high speed components into a single functional block as seen by the device designer.

  • Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive USB data

  • Data and clock recovery from serial stream on the USB bus

  • Holding registers to stage transmit and receive data

  • Supports direct disparity control for use in transmitting compliance pattern

  • 8b/10b encode/decode and error indication

  • 128b/132b encode/decode and error indication

  • Receiver detection

  • Low Frequency Period Signaling (LFPS) Transmission

INNOSILICON ADVANTAGES:

  • Small die size

  • Low pin counts

  • Low power consumption

  • Fully customizable

BLOCK DIAGRAM:

EXAMPLE APPLICATIONS:

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