MIPI C-PHY Tx and Rx(PHY & Controller)

The INNOSILICON MIPI C-PHY Combo TX integrates a MIPI? C-PHY 1.1 compatible PHY that supports up to 6.86Gbps/trio high speed data transmitter, plus a MIPI? low-power low speed transceiver that supports data transfer in the bi-directional mode. The C-PHY Combo TX is built in with a standard digital interface to talk to any third party Host controller.

The architecture supports connection of multiple data trios in parallel – up to 3 data trios can be connected to increase the total through-put, customizable to user determined configurations.

As a part of the INNOSILICON high speed PHY portfolio, including SATA/PCIE/XAUI/PCIe/HDMI/USB/HSIC/DDRn PHYs, the INNOSILICON MIPI C-PHY Combo TX is performance optimized, modular designed and easy to be integrated into any SoC.

Preassembled hard Macro PHY components are provided for immediate instantiation into an IC design.

KEY FEATURES:

  • Mixed-signal C-PHY mixed-signal hard-macro- HS/LP Transmitter and LP Receiver solution

  • Supports MIPI? Specification for C‐PHY Version 1.1

  • Integrated PHY Protocol Interface (PPI) supports interface to CSI, DSI and UniPro? MIPI? protocols

  • 3 trios in MIPI C‐PHY mode

  • 80 Msps to 3.0 Gsps symbol rate per trio in C‐PHY high speed mode. Equivalent to 182.8 Mbps to 6.86 Gbps per trio in C‐PHY high speed mode

  • Expandable to support 3 data trios, providing up to 20.58Gbps transfer rate under MIPI C-PHY HS mode

  • HS, LP and ULPS modes supported

  • Skew-Calibration supported

  • 10Mbps per lane in low-power mode

  • Unidirectional and  bi-directional modes supported

  • Automatic termination control for HS and LP modes

  • Tx/Rx Buffers with tunable On-Die-Termination and advanced equalization

  • Embedded ESD, boundary scan support logic

INNOSILICON ADVANTAGES:

  • Low power consumption

  • Fully customizable

  • Small area

  • All in one solution

  • Simple integration process

  • Available options include

    • Test chips and test boards

    • FPGA integration support

    • Chip level integration

BLOCK DIAGRAM:

EXAMPLE APPLICATIONS:

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